Wenjian Yu's Publications                                  

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  1. Wenjian Yu, Numerical Analysis and Algorithms (2nd Edition), Tsinghua Univ. Press, 2015 (in Chinese). available at Amazon.cn JD  
  2. Wenjian Yu and Xiren Wang, Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits, Springer (jointly with TUP), Apr. 2014, ISBN: 978-3-642-54297-8. available at Springer, Amazon  
  3. Wenjian Yu and Zeyi Wang, "Capacitance extraction," in Encyclopedia of RF and Microwave Engineering , K. Chang [Eds.] , John Wiley & Sons Inc., 2005. [manuscript proof]  
J40. Yu Gu, Wenjian Yu and Yaohang Li, "Efficient randomized algorithms for adaptive low-rank factorizations of large matrices," arXiv:1606.09402. 2016. [package]
J39. Khalid Al-jabery, Zhezhao Xu, Wenjian Yu, Donald C. Wunsch, II, Jinjun Xiong and Yiyu Shi, "Demand-side management of domestic electric water heaters using approximate dynamic programming," IEEE Trans. Computer-Aided Design, 36(5): 775-788, 2017 [pdf]
J38. Zhezhao Xu, Chao Zhang, and Wenjian Yu, "Floating random walk based capacitance extraction for general non-Manhattan conductor structures," IEEE Trans. Computer-Aided Design, 36(1): 120-133, 2017 [pdf][package]
J37. Hao Zhuang, Wenjian Yu, Shih-Hung Weng, Ilgweon Kang, Jeng-Hau Lin, Xiang Zhang, Ryan Coutts and Chung-Kuan Cheng, "Simulation algorithms with exponential integration for time-domain analysis of large-scale power delivery networks," IEEE Trans. Computer-Aided Design, 35(10): 1681-1694, 2016 [pdf]
J36. Wenjian Yu, Chensu Zhao, Siyu Yang, and Taotao Lu, "The application of boundary element method to the resistance calculation problem in designing flat panel displays," Journal of the Society for Information Display, 24(3): 177-186, 2016 [pdf][package]
J35. Chao Zhang, Wenjian Yu, Qing Wang, and Yiyu Shi, "Fast random walk based capacitance extraction for the 3-D IC structures with cylindrical inter-tier-vias," IEEE Trans. Computer-Aided Design, 34(12): 1977-1990, 2015 [pdf]
J34. Bolong Zhang, Wenjian Yu, and Chao Zhang, "Improved pre-characterization method for the random walk based capacitance extraction of multi-dielectric VLSI interconnects," International Journal of Numerical Modelling: Electronic Networks, Devices and Fields , 29(1): 21-34, 2016 [pdf]
J33. Qiang Yao, Zuochang Ye, Wenjian Yu, "An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs," Journal of Semiconductor, 36(8): 085006-1~7, 2015. [pdf]
J32. Y. Wang, T. T. Yang, J. C. Lao, R. J. Zhang, Y. Y. Zhang, M. Zhu, X. Li, X. B. Zang, K. L. Wang, Wenjian Yu, H. Jin, L. Wang, H. W. Zhu, "Ultra-sensitive graphene strain sensor for sound signal acquisition and recognition," Nano Research , 8(5): 1627-1636, 2015. [pdf]
J31. Xue-Xin Liu, Kuangya Zhai, Zao Liu, Kai He, Sheldon X.-D. Tan, and Wenjian Yu, "Parallel thermal analysis of 3D integrated circuits with liquid cooling on CPU-GPU platforms," IEEE Trans. Very Large Scale Integration Systems , 23(3): 575-579, 2015 [pdf]
J30. Kuangya Zhai, Wenjian Yu "The 2-D boundary element techniques for capacitance extraction of nanometer VLSI interconnects," International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 27: 656-668, 2014 [pdf]
J29. Wenjian Yu, Tao Zhang, Xiaolong Yuan, and Haifeng Qian, "Fast 3-D thermal simulation for integrated circuits with domain decomposition method," IEEE Trans. Computer-Aided Design, 32(12): 2014-2018, 2013 (listed as one of the TCAD popular papers) [pdf]
J28. Chao Zhang, Wenjian Yu, "Efficient space management techniques for large-scale interconnect capacitance extraction with floating random walks," IEEE Trans. Computer-Aided Design, 32(10): 1633-1637, 2013 [pdf][package]
J27. Wenjian Yu, Kuangya Zhai, Hao Zhuang, Junqing Chen, "Accelerated floating random walk algorithm for the electrostatic computation with 3-D rectilinear-shaped conductors," Simulation Modelling Practice and Theory, 34(5): 20-36, 2013 [pdf]
J26. Wenjian Yu, Hao Zhuang, Chao Zhang, Gang Hu, and Zhi Liu, "RWCap: A floating random walk solver for 3-D capacitance extraction of VLSI interconnects," IEEE Trans. Computer-Aided Design, 32(3): 353-366, 2013 (listed as one of the TCAD popular papers) [pdf][package]
J25. Xiao Li, Rujing Zhang, Wenjian Yu, Kunlin Wang, Jinquan Wei, Dehai Wu, Anyuan Cao, Zhihong Li, Yao Cheng, Quanshui Zheng, Rodney S. Ruoff, Hongwei Zhu, "Stretchable and highly sensitive graphene-on-polymer strain sensors," Scientific Reports , 2012, 2: art.-no: 870 [pdf]
J24. Wenjian Yu, Qingqing Zhang, Zuochang Ye, Zuying Luo, "Efficient statistical capacitance extraction of nanometer interconnects considering the on-chip line edge roughness," Microelectronics Reliability , 2012, 52(4): 704-710 [pdf]
J23. Z. Hao, S. X.-D. Tan, E. Tlelo-Cuautle, J. Relles, C. Hu, W. Yu, Y. Cai, and G. Shi, "Statistical extraction and modeling of inductance considering spatial correlation," Analog Integrated Circuits and Signal Processing, 2012, 73: 3-10 [pdf]
J22. Ling Zhang, Wenjian Yu, Yulei Zhang, et al. , "Analysis and optimization of low power passive equalizers for CPU-memory links," IEEE Trans. Components, Packaging and Manufacturing Technology , Vol. 1, No. 9 pp.1406-1420, Sep. 2011 [pdf]
J21. Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai and Gengsheng Chen, "Variational capacitance extraction and modeling based on orthogonal polynomial method," IEEE Trans. Very Large Scale Integration Systems , 2010, 18(11): 1556-1566 [pdf]
J20. Shan Zeng, Wenjian Yu, Xianlong Hong, and Chung-Kuan Cheng, "Efficient power network analysis with modeling of inductive effects," IEICE Trans. on Fundamentals , Vol. E93-A No. 6 pp.1196-1203, Jun. 2010 [pdf]
J19. Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, and Chung-Kuan Cheng, "Efficient power network analysis considering multidomain clock gating," IEEE Trans. Computer-Aided Design, 28(9): 1348-1358, 2009 [pdf]
J18. Shan Zeng, Wenjian Yu, Jin Shi, Xianlong Hong, Chung-Kuan Cheng, "Efficient partial reluctance extraction for large-scale regular power grid structures," IEICE Trans. on Fundamentals , Vol. E92-A No. 6 pp.1479-1484, Jun. 2009 [pdf]
J17. Wenjian Yu, Rui Shi, and Chung-Kuan Cheng, "Accurate eye diagram prediction based on step response and its application to low-power equalizer design," IEICE Trans. on Electronics , Vol. E92-C, No. 4 pp.444-452, Apr. 2009 [pdf][package]
J16. Wenjian Yu, Xiren Wang, Zuochang Ye, and Zeyi Wang, "Efficient extraction of frequency-dependent substrate parasitics using direct boundary element method," IEEE Trans. Computer-Aided Design, 2008, 27(8): 1508-1513 [pdf]
J15. Wenjian Yu, Changhao Yan, and Zeyi Wang, "Fast multi-frequency extraction of 3-D impedance based on boundary element method," Microwave and Optical Technology Letters, 2008, 50(8): 2191-2197 [pdf]
J14. Zuochang Ye, Wenjian Yu, and Zhiping Yu, "Analytical frequency-dependent model for transmission lines on RF-CMOS lossy substrates," Tsinghua Science and Technology, 2007, 12(6): 752-756 [pdf]
J13. Wenjian Yu, Changhao Yan, and Zeyi Wang, "A mixed surface integral formulation for frequency-dependent inductance calculation of 3D interconnects," Engineering Analysis with Boundary Elements, 2007, 31(10): 812-818 [pdf]
J12. Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Yang, Vijay Pitchumani, Chung-Kuan Cheng, "Efficient thermal via planning approach and its application in 3D floorplanning," IEEE Trans. Computer-Aided Design, 26(4): 645-658, 2007 [pdf]
J11. Xiren Wang, Wenjian Yu, and Zeyi Wang, "Efficient direct boundary element method for resistance extraction of substrate with arbitrary doping profile," IEEE Trans. Computer-Aided Design, 2006, 25(12): 3035-3042. [pdf]
J10. Changhao Yan, Wenjian Yu and Zeyi Wang, "Application of the complete multiple reciprocity method for 3D impedance extraction with multiple frequency points," Engineering Analysis with Boundary Elements, 2006, 30(8): 640-649. [pdf]
J9. Zuochang Ye, Wenjian Yu, and Zhiping Yu, "Efficient 3D capacitance extraction considering lossy substrate with multi-layered Green's function," IEEE Trans. Microwave Theory Tech., Vol. 54, No. 5, pp. 2128-2137, May 2006. [pdf]
J8. Xiren Wang, Wenjian Yu, and Zeyi Wang, Analytical-BEM coupling method for fast 3-D interconnect resistance extraction," Frontiers of Electrical and Electronic Engineering in China, Springer-Verlag Press and Higher Education Press, Vol. 1, No. 2, pp. 239-243, Apr. 2006. [pdf]
J7. Wenjian Yu, Mengsheng Zhang and Zeyi Wang, "Efficient 3-D extraction of interconnect capacitance considering floating metal-fills with boundary element method," IEEE Trans. Computer-Aided Design, Vol. 25, No. 1, pp. 12-18, Jan. 2006. [pdf] 
J6. Xiren Wang, Deyan Liu, Wenjian Yu and Zeyi Wang, "Improved boundary element method for fast 3-D interconnect resistance extraction," IEICE Trans. on Electronics, Vol. E88-C, No.2, pp.232-240, Feb. 2005.[pdf]
J5. Wenjian Yu, Zeyi Wang and Xianlong Hong, "Preconditioned multi-zone boundary element analysis for fast 3D electric simulation," Engineering Analysis with Boundary Elements, 2004, 28(9): 1035-1044. [pdf] 
J4. Wenjian Yu, Zeyi Wang, "Enhanced QMM-BEM solver for 3-D multiple-dielectric capacitance extraction within finite domain," IEEE Trans. Microwave Theory Tech., 2004, 52(2): 560-566. [pdf][package] 
J3. Taotao Lu, Zeyi Wang and Wenjian Yu, "Hierarchical block boundary-element method (HBBEM): a fast field solver for 3-D capacitance extraction," IEEE Trans. Microwave Theory Tech., 2004, 52(1): 10-19. [pdf] 
J2. Wenjian Yu, Zeyi Wang, "A fast quasi-multiple medium method for 3-D BEM calculation of parasitic capacitance," Computers & Mathematics with Applications , 2003, 45(12): 1883-1894. (cited by Mathematical Reviews) [pdf] 
J1. Wenjian Yu, Zeyi Wang, Jiangchun Gu, "Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM," IEEE Trans. Microwave Theory Tech., 2003, 51(1): 109-120. [pdf]
CJ16. 程康,叶佐昌,喻文健,"大规模RC网络的优化消去模型降阶算法",计算机辅助设计与图形学学报,第24卷,第11期,pp. 1506-1512, 2012年.[pdf]
CJ15. 胡超,喻文健,Sheldon Tan,"基于加权主元分析的统计互连寄生参数提取",计算机辅助设计与图形学学报,第22卷,第11期,pp. 1990-1997, 2010年.[pdf]
CJ14. 郑蓝舟,喻文健,尹航,王泽毅,"芯片级三维寄生电容的并行提取算法",计算机辅助设计与图形学学报,第20卷,第11期,pp. 1396-1402, 2008年.[pdf]
CJ13. 曾姗,喻文健,张梦生,洪先龙,王泽毅,"VLSI互连线频变K参数和频变电阻的有效提取算法",电子学报,第35卷,第11期,pp. 2072-2077, 2007年.[pdf]
CJ12. 巩方,喻文健,严昌浩,王泽毅,"三维互连阻抗的混合边界积分方程提取算法",计算机辅助设计与图形学学报,第19卷,第10期,pp. 1252-1258, 2007年。[pdf]
CJ11. 尹航,喻文健,陆涛涛,王泽毅,"重叠组合法的芯片级三维寄生电容提取及其并行实现",计算机辅助设计与图形学学报,第18卷,第2期,pp. 238-244, 2006年。[pdf]
CJ10. 喻文健,“互连线电容提取技术”,计算机世界报,2005年10月24日,第41期,B10-11。[pdf]
CJ9. 喻文健,王泽毅,“三维VLSI互连寄生电容提取的研究进展”,计算机辅助设计与图形学学报,第15卷,第1期,pp. 21-28, 2003年。 [pdf]
CJ8. 魏洪川,喻文健,杨柳,王泽毅,“基于K参数思想的快速三维互连电感电阻提取算法”,电子学报,第33卷,第8期, pp. 1365-1369,2005年。 [pdf]
CJ7. 魏洪川,喻文健,王泽毅,“快速计算频变互连电感电阻的加权平均法”,半导体学报,第26卷,第4期, pp. 846-850,2005年。 [pdf]
CJ6. 李漓,喻文健,王泽毅,洪先龙,“模拟集成电路三维互连电容的改进层次式提取”,计算机辅助设计与图形学学报,第17卷,第4期,pp. 651-656, 2005年。 [pdf]
CJ5. 王玉刚,喻文健,陆涛涛,王泽毅,“三维互连电容提取中复杂形体的通用几何处理方法”,计算机辅助设计与图形学学报,第16卷,第12期,pp. 1625-1630, 2004年。 [pdf]
CJ4. 王习仁,喻文健,王泽毅,“三维互连电阻解析与边界元耦合提取方法”,清华大学学报,第44卷,第9期,pp. 1277-1281, 2004年。 [pdf]
CJ3. 喻文健,王泽毅,王玉刚 等,“一种可适应复杂互连电容结构的边界元形体处理方法”, 半导体学报,第25卷,第2期,pp. 214-220, 2004年。 [pdf]
CJ2. 刘徳彦,喻文健,王泽毅,“复杂3-D寄生电容器的虚拟多介质切割”,计算机辅助设计与图形学学报,第15卷,第2期,pp. 180-186, 2003年。 [pdf]
CJ1. 陆涛涛,喻文健,王泽毅,“保形(Conformal)结构互连电容的BEM模拟”,计算机辅助设计与图形学学报,第13卷,第8期,pp. 684-689, 2001年。 [pdf]
C48. [IJCAI] Wenjian Yu, Yu Gu, Jian Li, Shenghua Liu, and Yaohang Li, "Single-pass PCA of large high-dimensional data," in Proc. the 26th International Joint Conference on Artificial Intelligence (IJCAI-17), , Melbourne, Austrila, Aug. 2017 (accepted) [package] Arxiv.org report #1704.07669.
C47. [ICSICT] Wenjian Yu, "Applications of Monte Carlo method to 3-D capacitance calculation and large matrix decomposition," in Proc. International Conference on Solid-State and Integrated Circuit Technology, Hangzhou, China. Oct. 2016 (invited paper) [pdf]
C46. [GLSVLSI] Zhezhao Xu, Wenjian Yu, Chao Zhang, Bolong Zhang, Meijuan Lu and Michael Mascagni, "A parallel random walk solver for the capacitance calculation problem in touchscreen design," in Proc. Great Lake Symposym of VLSI , Boston, USA, May 2016, pp. 99-104. [pdf]
C45. [DATE] Wenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang, and Luca Daniel, "Utilizing macromodels in floating random walk based capacitance extraction," in Proc. IEEE DATE , Dresden, Germany, Mar. 2016, pp. 1225-1230. (Best Paper Award! only 4 from 829 submissions) [pdf]
C44. [DAC] Hao Zhuang, Wenjian Yu, Ilgweon Kang, Xinan Wang, Chung-Kuan Cheng, "An algorithmic framework for efficient large-scale circuit simulation using exponential integrators," in Proc. Design Automation Conference , San Francisco, CA, USA, Jun. 2015, pp. 1-6. [pdf]
C43. [ICCAD] Wenjian Yu, Chao Zhang, Qing Wang, and Yiyu Shi, "Random walk based capacitance extraction for 3D ICs with cylindrical inter-tier-vias," in Proc. International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA, Nov. 2014, pp. 702-709. [pdf]
C42. [ICSICT] Wenjian Yu, "Two fast approaches for 3D thermal simulation of integrated circuits," in Proc. International Conference on Solid-State and Integrated Circuit Technology, Guilin, China. Oct. 2014, pp. 151-154. (invited paper) [pdf]
C41. [ASPDAC] Yuan Liang, Wenjian Yu, Haifeng Qian, "A hybrid random walk algorithm for 3-D thermal analysis of integrated circuits," in Proc. IEEE ASP-DAC, Singapore, Jan. 2014, pp. 849-854. [pdf]
C40. [ASPDAC] Chao Zhang, Wenjian Yu, "Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithm," in Proc. IEEE ASP-DAC, Singapore, Jan. 2014, 756-761. [pdf]
C39. [ASICON] Wenjian Yu, "RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnects," in Proc. International Conference on ASIC, Shenzhen, China. Oct. 2013, pp. 162-165. (invited paper) [pdf]
C38. [ASICON] Wenjian Yu, Siyu Yang, Qingqing Zhang, "Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D IC," in Proc. International Conference on ASIC, Shenzhen, China. Oct. 2013, pp. 1015-1018. [pdf]
C37. [DATE]Kuangya Zhai, Wenjian Yu, Hao Zhuang, "GPU-Friendly floating random walk algorithm for capacitance extraction of VLSI interconnects," in Proc. IEEE DATE , Grenoble, France, Mar. 2013, pp. 1661-1666. [pdf]
C36. [ICCCAS] Kuangya Zhai, Qingqing Zhang, Li Li, Wenjian Yu, "A 3-D parasitic extraction flow for the modeling and timing analysis of FinFET structures," in Proc. IEEE ICCCAS , Taichung, China, Aug. 2012, pp. 430-434. [pdf]
C35. [ASPDAC]Hao Zhuang, Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye, "Fast floating random walk algorithm for multi-dielectric capacitance extraction with numerical characterization of Green’s functions," in Proc. IEEE ASP-DAC , Sydney, Australia, Jan. 2012, pp. 377-382. [pdf]
C34. [DATE]Yuanzhe Xu, Wenjian Yu, Quan Chen, Lijun Jiang, Ngai Wong, "Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC," in Proc. IEEE DATE , Dresden, Germany, Mar. 2012, pp. 67-72. [pdf]
C33. [ASICON] Gang Hu, Wenjian Yu, Hao Zhuang, Shan Zeng, "Efficient floating random walk algorithm for interconnect capacitance extraction considering multiple dielectrics," Proc. International Conference on ASIC, Xiamen, China. Oct. 2011, pp. 896-899.
C32. [ASICON] Rubing Bai, Shan Zeng, Qingqing Zhang, Wenjian Yu, "An efficient solver for statistical capacitance extraction considering random process variations," Proc. International Conference on ASIC, Xiamen, China. Oct. 2011, pp. 602-605.
C31. [ASICON] Hao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye, "Numerical characterization of multi-dielectric Green’s function for floating random walk based capacitance extraction," Proc. International Conference on ASIC, Xiamen, China. Oct. 2011, pp. 361-364.
C30. [ASPDAC] Wenjian Yu, Chao Hu, and Wangyang Zhang, "Parallel statistical capacitance extraction of on-chip interconnects with an improved geometric variation model," in Proc. IEEE ASP-DAC , Yokohama, Japan, Jan. 2011, pp. 67-72. [pdf] [ppt]
C29. [ICCCAS] Weibing Gong, Wenjian Yu, Yongqiang Lu, et al., "A parasitic extraction method of VLSI interconnects for pre-route timing analysis," in Proc. IEEE ICCCAS , Chengdu, China, July 2010, pp. 871-875. [pdf]
C28. [ASPDAC] Wanping Zhang, Ling Zhang, Amirali Shayan, Wenjian Yu, Xiang Hu, Zhi Zhu, Ege Engin, Chung-Kuan Cheng, "On-chip power network optimization with decoupling capacitors and controlled-ESRs," in Proc. IEEE ASP-DAC , Taipei, Taiwan, Jan. 2010, pp. 119-124. [pdf].
C27. [DAC] Wenjian Yu, Chao Hu, and Wangyang Zhang, "Variational capacitance extraction of on-chip interconnects based on continuous surface model," in Proc. Design Automation Conference , San Francisco, CA, USA, Jul. 2009, pp. 758-763. [pdf]
C26. [SLIP] Wanping Zhang, Wenjian Yu, Xiang Hu, et al., "Predicting the worst-case voltage violation in a 3D power network," in Proc. International Workshop on System Level Interconnect Prediction (SLIP) , San Francisco, CA, USA, July 2009, pp. 93-98 [pdf].
C25. [ISQED] Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng, "Efficient power network analysis with complete inductive modeling," in Proc. 10th International Symposium on Quality Electronic Design , San Jose, CA, USA, Apr. 2009, pp. 770-775.
C24. [DATE] A. Shayan, X. Hu, H. Peng, C.-K. Cheng, Wenjian Yu, M. Popovich, T. Toms, X. Chen, "Reliability aware through silicon via planning for 3D stacked ICs," in Proc. ACM/IEEE Design, Automation & Test in Europe Conference, Nice, France, Apr. 2009, pp. 288-291. [pdf]
C23. [ASPDAC] Wanping Zhang, Yi Zhu, Wenjian Yu, et al., "Noise minimization during power-up stage for a multi-domain power network," in Proc. IEEE Asia South Pacific Design Automation Conference , Yokohama, Japan, Jan. 2009, pp. 391-396. [pdf]
C22. [ICCAD] Rui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, and Ernest S. Kuh, "Efficient and accurate eye diagram prediction for high speed signaling," in Proc. International Conference on Computer-Aided Design , San Jose, CA, USA, Nov. 2008, pp. 655-661. [pdf][package]
C21. [Hot'Inter] Ling Zhang, Wenjian Yu, Yulei Zhang, et. al, "Low power passive equalizer design for computer memory links," in Proc. the 16th Annual IEEE Symposium on High-Performance Interconnects (Hot Interconnects) , CA, USA, Aug. 2008, pp. 51-56.
C20. [DAC] Ling Zhang, Wenjian Yu, Haikun Zhu, et. al, "Low power passive equalizer optimization using tritonic step response," in Proc. Design Automation Conference , Anaheim, CA, USA, Jun. 2008 pp. 570-573. [pdf]
C19. [DATE] Wanping Zhang, Yi Zhu, Wenjian Yu, et. al, "Finding the worst voltage violation in multi-domain clock gated power network," in Proc. ACM/IEEE Design, Automation & Test in Europe Conference, Munich, Germany, Mar. 2008, pp. 537-540. [pdf] 
C18. [ISQED] Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, C.-K. Cheng, "Clock skew analysis via vector fitting in frequency domain," in Proc. 9th International Symposium on Quality Electronic Design, San Jose, CA, USA, Mar. 2008, pp. 476-479. [pdf]
C17. [DATE] Wangyang Zhang, Wenjian Yu, Zeyi Wang, Zhiping Yu, Rong Jiang, and Jinjun Xiong, "An efficient method for chip-level statistical capacitance extraction considering process variations with spatial correlation," in Proc. ACM/IEEE Design, Automation & Test in Europe Conference, Munich, Germany, Mar. 2008, pp. 580-585. [pdf]
C16. [ASPDAC] Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan, "Efficient techniques for 3-D impedance extraction using mixed boundary element method," in Proc. IEEE ASP-DAC , Seoul, Korea, Jan. 2008, pp. 158-163. [pdf]
C15. [ASPDAC] Xiren Wang, Wenjian Yu, Zeyi Wang, "A new boundary element method for multiple-frequency parameter extraction of lossy substrates," in Proc. IEEE ASP-DAC, Yokohama, Japan, Jan. 2007, pp. 62-67. (Best paper candidate)
C14. [ICSICT] Shan Zeng, Wenjian Yu, Xianlong Hong, Zeyi Wang, "An efficient 3D reluctance extractor for on-chip interconnects," the 8th International Conference on Solid-State and Integrated Circuit Technology, Oct. 2006, pp. 357-359. 
C13. [ICSICT] Wangyang Zhang, Wenjian Yu, Hong Liu, Zeyi Wang, "Hierarchical h-adaptive computation of VLSI interconnect capacitance with QMM acceleration," the 8th International Conference on Solid-State and Integrated Circuit Technology, Oct. 2006, pp. 1438-1440
C12. [ICSICT] Lanzhou Zheng , Wenjian Yu, and Zeyi Wang, "Hierarchical block boundary element method for substrate resistance calculation," the 8th International Conference on Solid-State and Integrated-Circuit Technology, Oct. 2006, pp. 2095-2097 
C11. [ICSICT] Wenjian Yu, Lei Zhang, Xiren Wang, and Zeyi Wang, "An incremental boundary element method for the variation-aware library-building procedure of capacitance extraction," the 8th International Conference on Solid-State and Integrated Circuit Technology, Oct. 2006, pp. 1435-1437
C10. [ISQED] Changhao Yan, Wenjian Yu, and Zeyi Wang, "A mixed boundary element method for extracting frequency-dependent inductances of 3D interconnects," in Proc. 7th International Symposium on Quality Electronic Design , San Jose, CA, USA, Mar. 2006, pp. 709-714. (Best paper candidate)
C9. [ASPDAC] Mengsheng Zhang, Wenjian Yu, Yu Du and Zeyi Wang, "An efficient algorithm for 3-D reluctance extraction considering high frequency effect," in Proc. IEEE ASP-DAC, Yokohama, Japan, Jan. 2006, pp. 521-526.
C8. [ASPDAC] Xiren Wang, Wenjian Yu, Zeyi Wang, "A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles," in Proc. IEEE ASP-DAC, Yokohama, Japan, Jan. 2006, pp. 683-688.
C7. [SISPAD] Hongchuan Wei, Wenjian Yu and Zeyi Wang, "A fast algorithm for 3-D inductance extraction based on investigation of open-circuit current," International Conference on Simulation of Semiconductor Processes and Devices , Tokyo, Japan, Sep. 2005, pp. 203-206.
C6. [GLSVLSI] Xiren Wang, Wenjian Yu and Zeyi Wang, "An improved direct boundary element method for substrate coupling resistance extraction," in Proc. Great Lake Symposym of VLSI , Chicago, US, Apr. 2005, pp. 84-87.
C5. [ASPDAC] Xiren Wang, Wenjian Yu and Zeyi Wang, "Substrate resistance extraction with direct boundary element method," in Proc. IEEE ASP-DAC , Shanghai, China, Jan. 2005, pp. 208-211.
C4. [ICCCAS] Wenjian Yu, Li Li, Zeyi Wang and Xianlong Hong, "Improved 3-D hierarchical interconnect capacitance extraction for the analog integrated circuit," International Conference on Communications, Circuits and Systems , June 2004, pp. 1305-1309.
C3. [ICCD] Wenjian Yu, Zeyi Wang and Xianlong Hong, "Enhanced QMM-BEM solver for 3-D finite-domain capacitance extraction with multilayered dielectrics", IEEE 21st International Conference on Computer Design , USA, Oct. 2003, pp. 58-63.
C2. [ASICON] Xiren Wang, Wenjian Yu, Deyan Liu, Zeyi Wang, "Fast extraction of 3-D interconnect resistance: numerical-analytical coupling method," Proc. 5th International Conference on ASIC , Beijing, China. Oct. 2003, pp. 315-318.
C1. [ASPDAC] Wenjian Yu, Zeyi Wang, "An efficient quasi-multiple medium algorithm for the capacitance extraction of actual 3-D VLSI interconnects," in Proc. IEEE Asia South Pacific Design Automation Conference , Yokohama, Japan, Jan. 2001, pp. 366-371. (Best paper candidate) 
CC4. 张青青,喻文健,骆祖莹,"圆柱形硅通孔的二维解析电容模型",第17届全国计算机辅助设计与图形学学术会议(CAD/CG'2012),山东青岛,2012年7月,pp. 522-526 (Best student paper candidate) 
CC3. 汤启明,喻文健,许静宇,孙海洋,"基于库查找的差分线网匹配检测算法",第17届全国计算机辅助设计与图形学学术会议(CAD/CG'2012),山东青岛,2012年7月,pp. 527-531  
CC2. 胡超,喻文健,"面向统计互连电容提取的随机变动几何建模",第16届全国计算机辅助设计与图形学学术会议(CAD/CG'2010),山西太原,2010年7月,pp. 644-652 (Best student paper award) 
CC1. 刘志,戴挺,喻文健,"三维随机行走电容提取算法的实现",第16届全国计算机辅助设计与图形学学术会议(CAD/CG'2010),山西太原,2010年7月,pp. 699-706 
  1. Chinese version of Insight Through Computing: A MATLAB Introduction to Computational Science and Engineering (by Charles F. Van Loan, K.-Y. Daisy Fan, SIAM, 2010), W. Yu [Eds.], Tsinghua Univ. Press, 2012  
  2. Chinese version of Numerical Computing with MATLAB (by Cleve B. Moler, SIAM, 2004), W. Yu [Eds.], China Machine Press, 2006  
  3. Chinese version of Hardware and Computer Organization: The Software Perspective (by Arnold S. Berger, Newnes, 2005), W. Wu, W. Yu, S. Deng, S. Wu [Eds.], China Machine Press, 2007  
  4. Chinese version of Interconnect Analysis and Synthesis (by C.-K. Cheng, J. Lillis, S. Lin, N. Chang, John-Wiley, 2000), W. Yu and N. Xu [Eds.], Tsinghua Univ. Press, 2008  
  5. Chinese version of Design of High-Performance Microprocessor Circuits (by A. Chandrakasan, W. J. Bowhill, F. Fox, IEEE Press, 2001), X. Yuan, W. Yu and W. Wu [Eds.], China Machine Press, 2010
  6. Chinese version of Interconnect Technology and Design for Gigascale Integration (by J. A. Davis, J. D. Meindl, Kluwer Academic Publishers, 2003), Z. Luo, Z. Ye, Y. Lv and W. Yu [Eds.], China Machine Press, 2010